set active_design "bypass_fifo";                     
# Top module name
set clock_name "clk";                           
# Name of clock
set reset_name "rst_n";                      
# Name of reset


#200M
set clk_period 1
#set clk_period [expr [::tcl::mathfunc::floor [expr 10000 * 1000.0/1000 ] ] / 100000] #1000MHz
# Desired Clock Period = 1000/Frequence
set clk_uncertainty_setup [expr $clk_period/200];

set clk_latency [expr $clk_period/5];                         
# Network Latency of clock
